1. Field of the Invention
The present invention relates a general-purpose logic cell array in which general-purpose logic cells are formed in an array, and an ASIC (Application Specific Integrated Circuit) using the same.
2. Description of the Related Art
Conventionally, a cell array is known in which a plurality of cells are formed in a lower layer and arranged in an array. By forming a wiring layer for connecting the plurality of cells, a logic circuit with a desired function is formed. Thus, a semiconductor integrated circuit can be manufactured speedily. For example, Japanese Laid Open Patent Application (JP-A-Heisei 11-238850) discloses a cell array of a gate array type in which basic cells are arranged in an array. In this cell array, as shown in FIG. 1, basic cells are arranged in an array on a semiconductor substrate, and each of the basic cells has a plurality of transistors. Exclusive use cells for flip-flops are provided separately from the basic cells. In case that a logic circuit is formed using the cell array, the exclusive use cell is used for the flip-flop contained in the logic circuit. When the exclusive use cell is lack, a flip-flop is formed using the transistors of the basic cell.
In the cell array of the gate array type, a lower layer or a wafer with no wiring line layer is provided. The cells are connected in accordance with a pattern designed by a user and the logic circuit is manufactured.
Also, a cell array is known in which cells of general-purpose logic modules such as a mask programmable functional block based gate array and general FPGA (Field Programmable Gate Array) are arranged in an array. For example, as such a cell array, U.S. Pat. No. 5,684,412 discloses “CELL FORMING PART OF A CUSTOMIZABLE ARRAY”. The general logic module used in the cell array is composed of a NAND circuit 50, a 2-input multiplexer (A) 51, a 2-input multiplexer (A) 52, a 2-input multiplexer (LARGE) 53, as shown in FIG. 2. The general logic module is optimized such that an input capacity of an element of an input stage is small, and a drive capability of an element of an output stage is large.
As described above, the general-purpose logic module is a semiconductor integrated circuit in which basic circuits called general-purpose logic cells are formed in an array formed on a semiconductor substrate. The basic circuit is formed by electrically connecting MOS transistors in a general-purpose logic cell by a lower wiring line layer and a desired logic circuit is formed by electrically connecting the above general-purpose logic cells in the array by an upper wiring line layer. An ASIC (Application Specific Integrated Circuit) is manufactured using the general-purpose logic modules. The basic circuit is generally composed of a logic circuit having relatively small functions like an inverter circuit, a NAND circuit, a NOR circuit, or a multiplexer.
If the general-purpose logic modules are used, a wiring line pattern of the upper wiring line layer is designed to realize the desired logic circuit, and a lithography mask is formed using the wiring line pattern. Then, the upper wiring line layer is formed on the semiconductor substrate through a semiconductor manufacturing process to connect the general-purpose logic modules. Thus, a semiconductor chip with a desired logic circuit is formed.
The semiconductor substrate on which the general logic modules are formed is used as follows. For example, a semiconductor manufacturer opens to a user, the information of the semiconductor substrate. The user designs the desired logic circuit based on the opened information and requests the semiconductor manufacturer to manufacture a semiconductor chip to realize the desired logic circuit. The semiconductor manufacturer automatically designs the wiring line pattern of the upper wiring line layer based on the logic circuit received from the user and manufactures the semiconductor chip through the above mentioned process.
A cell array in which such a general logic module is used as a cell has a merit that a manufacturing term from the design of the logic circuit by the user to the completion of the semiconductor chip becomes short, compared with the cell array of above-mentioned gate array type.
However, the cell array disclosed in the above-mentioned Japanese Laid Open Patent Application (JP-A-Heisei 11-238850) is of a gate array type. Therefore, the basic cell as the lower layer is composed of transistors and only a diffusion region and gate regions are formed and wiring lines are not formed. When the logic circuit instructed from the user is formed using the cell array, it is necessary to carry out all the connections in the upper and lower wiring line layers, such as the wiring lines for the power and ground of the basic cell, and the wiring lines connecting between the basic cells. For this reason, the wiring line resource becomes bottom neck.
Also, in a cell array disclosed in the above-mentioned U.S. Pat. No. 5,684,412, a cell consisting of one kind of a general logic module is arranged in an array as the lower layer. A wiring line layer is formed on the lower layer to connect the general logic modules. Thus, a logic circuit instructed by the user is formed. For this reason, the wiring line resource to be used is few, compared with the cell array of the above-mentioned gate array method.
Also, in the general-purpose logic array, an optimization of the input stage and output stage of each general logic module is accomplished as described above. However, because only one kind of the general logic module exists, an optimization cannot be achieved from the viewpoints of the nature of the logic circuit instructed by the user, i.e., which of a combinational circuit, a sequential circuit and a drive circuit is most used. For this reason, when the logic circuit is formed by combining the general logic modules, the power consumption, the input capacity, and the drive ability and so on can not be optimized.